1. Field of the Invention
The present invention relates to a semiconductor device and fabricating method thereof that can reduce a drain leakage current generated from a horizontal electric field of a gate electrode.
2. Discussion of the Related Art
Generally, semiconductor devices are being highly integrated, whereby transistors are decreasing in size. Specifically, until relatively recently, drain leakage current has been primarily generated from a vertical electric field. Yet, transistor channel lengths in semiconductor devices have been reduced in accordance with an increased integration degree, whereby the main concern about the leakage current is that caused by a horizontal electric field.
A low-voltage N-channel metal oxide semiconductor field effect transistor device generally employs an LDD (lightly doped drain) junction structure to enhance the hot-carrier effect. The hot-carrier effect is sometimes also called high-temperature electron effect or hot electron effect. If a channel length of a transistor is shortened without changing a voltage applied between a drain and source, an electric field within a depletion layer provided to a drain end of the channel increases. Hence, electrons are accelerated at high speed to collide with atoms, thereby bringing about an avalanche phenomenon. The highly accelerated electrons may also enter a gate oxide layer to be trapped therein, thereby varying a threshold voltage of the transistor, as well as causing leakage current, making the operation of the transistor unstable. In order to weaken the electric field within the depletion layer of the drain, a drain layer doped lighter than the drain is further provided to the drain, which is called LDD.
A method of fabricating a semiconductor device having a conventional LDD is explained with reference to the attached FIGS. 1A to 1E.
Referring to FIG. 1A, an oxide layer 2 and a conductive layer 3 are sequentially stacked on a semiconductor substrate. Namely, the oxide layer 2 for forming a gate insulating layer and the conductive layer 3 for forming a gate electrode are stacked on the semiconductor substrate 1 provided with a device isolation area (not shown), in turn. The device isolation area can be formed by LOCOS (local oxidation of silicon) or STI (shallow trench isolation).
Referring to FIG. 1B, a gate electrode 4 is formed by patterning. Namely, the conductive layer 3 and the oxide layer 2 shown in FIG. 1A are photolithographically patterned and etched using a mask to form the gate electrode 4 and the gate insulating layer 3 to provide the structure shown.
Referring to FIG. 1C, LDD regions 5 are formed. Namely, impurity ions are implanted into an exposed surface of the semiconductor substrate 1 at a light dopant density to form the LDD regions 5 in the vicinity of the gate electrode 4. In doing so, N-type impurities are lightly implanted for the LDD regions of an N-type transistor, whereas P-type impurities are lightly implanted for the LDD regions of a P-type transistor.
Referring to FIG. 1D, sidewall spacers 6 are formed on sidewalls of the gate electrode 4. Namely, an oxide layer and a nitride layer are blanket deposited onto the structure of FIG. 1C and anisotropically etched to form the spacer oxide 6a and spacer nitride 6b on the sidewalls of the gate electrode. Alternatively, the spacer 6 can be formed from a single layer of either nitride or oxide. Yet, a dual layer, as shown in the drawing, is frequently used to enhance a leakage current characteristic (e.g., reduce the leakage current) of a highly integrated device.
Referring to FIG. 1E, a source and drain configuring the transistor are formed. Namely, impurity ion implantation is carried out on the resultant structure shown in FIG. 1D to form the source/drain terminals 7 of the transistor. In doing so, the source/drain 7 are doped with either N- or P-type impurity ions as well. Specifically, photoresist is coated on the result structure shown in FIG. 1D, a PMOS area is exposed only, and p+ ion implantation is then heavily carried out thereon to form p+ source and drain. Thereafter, a photoresist pattern exposing an NMOS area only is formed and n+ ion implantation is then heavily carried out thereon to form n+ source and drain.
Yet, the semiconductor device fabricated by the above-explained method is disadvantageous in that the drain leakage current caused by the electric field of the gate electrode in a horizontal direction may be increased. Namely, in case of applying high and low voltages to gate and drain electrodes, respectively, a leakage current may be generated between the drain and the semiconductor substrate by band-to-band tunneling in a region of overlap between the gate electrode and the lightly doped drain (LDD) region (the “overlap region”).
To reduce the leakage current, the heavily doped impurities are prevented from diffusing into the LDD region, or a width of the sidewall spacer is increased to extend the LDD. However, limitations are put on the current equipment in lowering the density of the LDD region. And, in the case of extending the spacer width, the operational speed and/or integration degree of the device may be lowered (e.g., the transistor consumes a greater area and may take a longer time to become conducting or non-conducting, as the case may be).
Meanwhile, Korean Patent Public Laid-Open No. 2000-43209 discloses a semiconductor device fabricating method. First, in fabricating CMOS provided with buried PMOS and NMOS, light impurity ion implantation is carried out twice to form LDD regions in junctions between a semiconductor substrate and source/drain regions in a part in the vicinity of a surface of the semiconductor substrate and another part lower than the surface of the semiconductor substrate. The source/drain regions are then formed. Hence, it is able to prevent a punch-thru path from occurring in the buried PMOS, whereby characteristics and reliability of the semiconductor device can be enhanced. Yet, such a method needs a process of forming a separate spacer for providing the second LDD regions, thereby complicating the manufacturing process.
U.S. Pat. No. 6,586,306 (Lee, et al.) discloses a CMOS semiconductor device fabricating method. First of all, in photolithography for forming LDD regions of an input/output device having a gate insulating layer thicker than that of a core device, portions of source/drain regions in the vicinity of an edge of a device isolation insulating layer in the core device area are partially exposed. The partially exposed portions are simultaneously ion-implanted on performing ion implantation for forming the LDD regions of the input/output device, whereby a deep junction is formed in the vicinity of the device isolation insulating layer without affecting a channel region of the core device to prevent junction leakage current from increasing. Hence, the process yield and reliability of device operation can be enhanced. Yet, such a method needs a separate mask for forming the second LDD regions, thereby complicating the manufacturing process and increasing its cost.